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cn8478/cn8474a/ cn8472a/cn8471a evaluation module user s guide n8478ug1a august 16, 1999 preliminary review 8/16/99 1600
n8478ug1a conexant preliminary information/conexant proprietary and confidential information provided by conexant systems, inc. (conexant) is believed to be accurate and reliable. however, no responsibility i s assumed by conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use . no license is granted by implication or otherwise under any patent rights of conexant other than for circuitry embodied in conexan t products. conexant reserves the right to change circuitry at any time without notice. this document is subject to change withou t notice. conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a conexant product can reasonably be expected to result in personal injury or death. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages resulting f rom such improper use or sale. conexant and the conexant symbol are trademarks of conexant systems, inc. product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. all other marks mentioned herein are the property of their respective holders. ? 1999 conexant systems, inc. printed in u.s.a. all rights reserved reader response: to improve the quality of our publications, we welcome your feedback. please send comments or suggestions via e-mail to conexant reader response@conexant.com . sorry, we can't answer your technical questions at this address. please contact your local conexant sales office or local field applications engineer if you have technical questions. preliminary review 8/16/99 1600
n8478ug1a conexant iii preliminary information/conexant proprietary and confidential table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1.0 product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 1 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 1.3 online documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 2.0 installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 contents and requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 board installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.3 software installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3.1 installing the cn8478 evm toolbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3.2 uninstalling the cn8478 evm toolbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3.3 driver setup (oemsetnt.inf, rokwan.sys) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4 windows nt architectural model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.4.1 network driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.4.2 windows nt registry entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.4.3 software block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.4.4 protocol structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.4.5 generic queries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.5 api_t1e1readregistermap() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.5.1 api_t1e1configuration() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.5.2 api_readdevicestatistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.5.3 api_read_device_register() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 3.0 hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 expansion bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 2 3.3 pci bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.4 serial buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 preliminary review 8/16/99 1600
table of contents n8478ug1a evaluation module user?s guide iv conexant n8478ug1a preliminary information/conexant proprietary and confidential 3.5 t1 / e1 line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.6 bt8370 clocking options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 4.0 software architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 software block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 nt ndis interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.2 cn8478 driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.1.3 bt8370 driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.3 apis?backdoor mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.1 backdoor read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.3.2 backdoor write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 4.3.3 backdoor initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.3.4 backdoor action start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.3.5 backdoor action stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 4.3.6 backdoor action configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.3.7 backdoor loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 5.0 using the cn8478 evm toolbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 starting the cn8478 evm toolbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 main menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3 application level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.1 application level menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.3.2 loopback tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 5.3.3 summary of application level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4 logical level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 0 5.4.1 cn8478 logical level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 5.4.2 bt8370 logical level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.4.3 summaries of logical level windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 5.5 physical level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.5.1 register area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.5.2 source, values, and destination area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 5.5.3 summary of physical level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14 preliminary review 8/16/99 1600
n8478ug1a table of contents evaluation module user?s guide n8478ug1a conexant v preliminary information/conexant proprietary and confidential 6.0 list of acronyms and abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 appendix a: sample connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 appendix b: bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 appendix c: mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . c-1 appendix d: circuit schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . d-1 appendix e: circuit board drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e-1 sales offices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 preliminary review 8/16/99 1600
table of contents n8478ug1a evaluation module user?s guide vi conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a list of figures evaluation module user?s guide n8478ug1a conexant v preliminary information/conexant proprietary and confidential list of figures figure 2-1. windows nt architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 figure 2-2. title? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 figure 2-3. title? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 figure 2-4. software block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 figure 3-1. bt8474 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 figure 3-2. expansion bus memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 figure 3-3. serial bus between musycc and t1 transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 figure 3-4. bt8370 serial clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 figure 4-1. software block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 figure 4-2. backdoor structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 figure 4-3. structure of data in shared memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-8 figure 5-1. main menu of the cn8478 evm toolbox. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 figure 5-2. application level window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 figure 5-3. options menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 figure 5-4. explore messages window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 figure 5-5. pci configuration window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 figure 5-6. bt8370 loopback test area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 figure 5-7. cn8478 loopback tests area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-6 figure 5-8. example of test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 figure 5-9. channel statistics window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7 figure 5-10. monitor errors display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 figure 5-11. transmit and receive information area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -8 figure 5-12. bt847x logical level window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 figure 5-13. bt8370 logical level window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 figure 5-14. cn8478 registers window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13 figure a-1. typical development environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .a-1 preliminary review 8/16/99 1600
list of figures n8478ug1a evaluation module user?s guide vi conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a list of tables evaluation module user?s guide n8478ug1a conexant vii preliminary information/conexant proprietary and confidential list of tables table 4-1. read shared memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-2. read shared memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-3. read shared memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 table 4-4. read bt847x register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 table 4-5. read bt847x register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 table 4-6. read bt8370 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 table 4-7. read bt8370 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 table 4-8. read message maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 table 4-9. read message data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 table 4-10. read pci configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 table 4-11. write bt8370 register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 table 4-12. write bt847x register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 table 4-13. write bt847x register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10 table 4-14. card initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 table 4-15. bt847x initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 table 4-16. bt847x loopback without self test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-11 table 4-17. stop bt847x loopback test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 table 4-18. configuration of bt847x time slot assignments and channel protocols . . . . . . . . . . . . . . 4-13 table 4-19. configure loopback message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 table 4-20. run bt8370 loopback. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 table 4-21. stop bt8370 loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 table 5-1. summary of application level window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -9 table 5-2. summary of cn8478 logical level window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 table 5-3. summary of bt8370 logical level window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 preliminary review 8/16/99 1600
list of tables n8478ug1a evaluation module user?s guide viii conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a conexant 1-1 preliminary information/conexant proprietary and confidential 1 1.0 product overview 1.1 introduction this document describes the requirements and plan to build an evaluation module (evm) for cn8478/cn8474a/cn8472a/cn8471a (musycc). this document captures evm requirements from marketing and engineering for the specification, design, software development, integration, and production phases. as a marketing collateral, the evm is sold or otherwise made available to customers for the purposes of demonstrating features and accelerating customers? time to market. the cn8478 evm is a demonstration and test platform that allows system developers and product designers to test and evaluate the functionality and performance of the cn8478 chip. the cn8478 evm is an eight-channel synchronous communication module with t1 and e1 interfaces. each physical line is supported by the bt8370 t1/e1 transceiver, which provides support for data link maintenance, and one high-level data link control (hdlc) controller supported by the cn8478, which formats up to 256 hdlc channels. the cn8478 evm software is implemented under the windows nt 4.0 operating system as a network driver interface specification (ndis) miniport driver. the winnt driver code is available with the cn8478 evm product. the cn8478 evm toolbox is divided into three levels: physical level, logical level, and application level. it is used to perform several functions: loopback testing reading channel statistics reading pci configurations configuring dynamic hyperchanneling reading from and writing to device registers reading from and writing to shared memory viewing register map performance monitoring preliminary review 8/16/99 1600
1.0 product overview n8478ug1a 1.2 reference documents evaluation module user?s guide 1-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential 1.2 reference documents these related documents are available from conexant, network access products division: cn8478/cn8474a/cn8472a/cn8471a ?multichannel synchronous communications controller (musycc) bt8370?fully integrated t1/e1 framer and line interface other documents: microsoft ddk/ndis drivers 1.3 online documentation technical product documentation for the cn8478 and bt8370 is available from conexant information website. 1 go to http://www.conexant.com/techinfo. 2 after registering, select network access. 3 on the network access page, select the device number. alternative component selection and specification for the bill of materials are also provided in portable document format (pdf) in the same directory. preliminary review 8/16/99 1600
n8478ug1a conexant 2-1 preliminary information/conexant proprietary and confidential 2 2.0 installation 2.1 contents and requirements the following items are included in your packing list: cn8478 evaluation module (evm) board cn8478 evm cd software cn8478/cn8474a/cn8472a/cn8471a datasheet bt8370 datasheet cn8478 evaluation module user?s guide to use the cn8478 evm, you need the following system: ibm pc or compatible with 32 mb ram memory and a controller card (pci 32 bit, 2.0 or higher) windows nt server 4.0 operating system a protocol analyzer (optional) your telecom equipment to be tested to use the online help, you need the following software: acrobat reader 3.0 2.2 board installation to install the board, follow these steps: 1. power down the computer and follow the manufacturer?s directions to remove the cover from your computer. 2. locate an empty pci bus slot and plug in the cn8478 evm board. 3. plug the protocol analyzer into a t1/e1 port; otherwise, leave the t1/e1 ports disconnected. 4. follow the manufacturer?s directions to replace the cover on your computer and power up. preliminary review 8/16/99 1600
2.0 installation n8478ug1a 2.3 software installation evaluation module user?s guide 2-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential 2.3 software installation copy the software for the driver and the toolbox from the supplied cd onto the hard drive. 2.3.1 installing the cn8478 evm toolbox run setup.exe from the cd path: projects/evm847x\setup.exe . the installation batch file adds the cn8478 evm toolbox to the program menu. 2.3.2 uninstalling the cn8478 evm toolbox to uninstall cn8478 evm toolbox, run add/remove programs in the control panel window and select cn8478 evm toolbox. this removes all files and information from the registry entries. 2.3.3 driver setup (oemsetnt.inf, rokwan.sys) each ndis driver must provide a setup file, called an oemsetnt . inf script , containing information about how the driver is loaded and its relationships to other network drivers. during system setup, the network is configured on the machine, and the setup file for each network component writes to the registry. this describes how these components fit within the set of installed network drivers that are bound into the network stack. the new network driver is the conexant wan adapter, rockwan.sys . to install the driver, perform the following steps: 1. from the start menu, choose settings and control panel. 2. from the control panel, double click the network icon. 3. from the network window, choose adapters. 4. in the adapters screen, click add. this opens a window with all network adapters in the system. click havedisk. 5. type the path: projects/windows driver/wmp-nt40 , and click ok. this path contains the driver file (i.e. oemsetnt.inf, rokwan.sys). if the path is incorrectly typed, this error message is received: ?setup message: setup cannot find oemsetup.inf or osmsetnt.inf. please type a new path to the oemsetup.inf file. ? 6. the next window is select oem option window. choose conexant wan adapter. click ok. 7. the next window is the conexant wan miniport driver bus location screen. select the pci bus type. select the bus number where the pci bus is located. click ok. the following message is displayed: ?rockwell wan setup is completed. 8. click ok. 9. to set up the bindings of the configuration, click the close button from network windows. 10. to complete installation, shut down and restart your computer. preliminary review 8/16/99 1600
n8478ug1a 2.0 installation evaluation module user?s guide 2.4 windows nt architectural model n8478ug1a conexant 2-3 preliminary information/conexant proprietary and confidential 2.4 windows nt architectural model the generic architecture of the windows nt cn8478 evm is defined as a modular system. figure 2-1 illustrates the windows nt architecture as a modular system. hardware platform = pci card and mic/wah adaptor, which contains the cn8478 part. where: hardware abstraction layer (hal) virtualizes hardware interfaces. kernel manages the basic operation of windows nt. the activities the kernel schedules are called threads, the most basic entity in the system that can be scheduled. threads are defined in the context of the process. a process is defined as an address space, a set of objects visible to the process, and a set of threads that run in the context of the process. nt executive system services interface consists of several distinct software components that offer their services both to user-mode process and to one another. these executive components are independent and communicate through well-defined interfaces as illustrated in figure 2-2 . figure 2-1. windows nt architecture nt executive kernel hardware abstraction layer (hal) hardware platform 8478_049 preliminary review 8/16/99 1600
2.0 installation n8478ug1a 2.4 windows nt architectural model evaluation module user?s guide 2-4 conexant n8478ug1a preliminary information/conexant proprietary and confidential the backdoor mechanism (messages) communicates to the i/o manager in order to query and get data. the i/o manager converts the i/o request from user and kernel-mode threads into properly sequenced calls to the nic driver routine. through the backdoor mechanism, an interface is defined so all device drivers can communicate with the application (gui) in the same way. therefore, the application need not know any specific device drivers? apis that will be called in the device-specific part of nic driver. 2.4.1 network driver the cn8500 evm nic driver is a network device driver, implemented as a component in the i/o architecture. windows nt includes integrated networking capabilities and support for distributed applications. the networking level is supported by a series of network drivers, illustrated in figure 2-3 . figure 2-2. nt executive components nt executive object mgr config mgr process mgr security monitor local proc call virtual memory mgr i/o mgr 8478_050 preliminary review 8/16/99 1600
n8478ug1a 2.0 installation evaluation module user?s guide 2.4 windows nt architectural model n8478ug1a conexant 2-5 preliminary information/conexant proprietary and confidential 2.4.2 windows nt registry entry setup?loads new configuration data to the registry. recognizer?places hardware configuration in your registry when you start a computer running windows nt. windows nt kernel?extracts information from the registry (such as which device drivers to load and their load order) during the system startup. device drivers?send and receive load parameters and configuration data from the registry. a device driver must report system resources it uses, such as hardware interrupts and dma channels, so the system can add this information to the registry. application and device drivers can read this registry information to provide users with smart installation and configuration programs. administrative tools?can be used to modify configuration data. agenda? process?an address space, set of objects (resources) visible to the process, and a set of threads that run in the context of the process. a thread is most the basic schedulable entity in the system. the process has its own set of registers, its own kernel stack, a thread environment block, and user stack in the address space of its process. kernel?schedules threads to be executed. the threads are defined in the context of the process which defines an address space, a set of objects visible to the process, and a set of threads that runs in the context of the process. the kernel manages two types of objects: figure 2-3. networking level 8478_051 provider interface/server transport driver interface ndis interface network network adapter card drivers and miniport drivers preliminary review 8/16/99 1600
2.0 installation n8478ug1a 2.4 windows nt architectural model evaluation module user?s guide 2-6 conexant n8478ug1a preliminary information/conexant proprietary and confidential 1. dispatcher objects have a signal state, which includes the following: events, mutants, semaphores, threads and timers. 2. control objects control the operation of the kernel. 2.4.3 software block diagram the diagram in figure 2-4 indicates the basic software blocks . figure 2-4. software block diagram 8478_052 application gui t1/e1 t3/e3 hdlc protocol structure update device io control sys file loaded in the os device independent handler (device io control) or (serial driver) send_message winnt device specific (id_device) handler protocol structure message (parser) hpi hdlc a1 b1 c1 hpi t1/e1 hpi t3/e3 user mode kernel mode i/o manager i/o control thread preliminary review 8/16/99 1600
n8478ug1a 2.0 installation evaluation module user?s guide 2.4 windows nt architectural model n8478ug1a conexant 2-7 preliminary information/conexant proprietary and confidential 2.4.4 protocol structure 2.4.4.1 backdoor structure the backdoor structure is a message protocol communication between the driver and the gui. for winnt, this structure is passed to the deviceiocontrol which passes the control to the service access point (sap) which is the winnt device-specific function. the implementation of the backdoor structure is as follows: typedef struct tbackdoor { dword keycode; / * per device* dword reqcode; / *request code*/ dword reqsubcode; /* subrequest code*/ dword totalsize; /* backdoor total structure *./ dword neededsize; dword resultcode; dword param1; dword param2; dword param3; dword param4; dword param5; dword param6; dword vparam1size; //v for variable dword vparam1offset; dword vparam2size; dword vparam2offset; dword vparam3size; dword vparam3offset; dword vparam4size; dword vparam4offset; byte data[4]; }back_door, *pback_door; 2.4.5 generic queries read_shared_memory read_shared_memory_location 2.4.5.1 t1/e1 device driver the backdoor structure in order to provide protocol message communication between the application level and the device driver. preliminary review 8/16/99 1600
2.0 installation n8478ug1a 2.5 api_t1e1readregistermap() evaluation module user?s guide 2-8 conexant n8478ug1a preliminary information/conexant proprietary and confidential 2.4.5.2 t1/e1 hpi primitive functions system and backdoor initialization pbd->parm1 = port_number (group number) pbd->reqcode = backdoor _read pbd->reqsubcode = backdor_read_xxxx_regiter_map pbd->needsize = sizeof(backdoor) + sizeof(grp_reg_map) pdb->totolsize = sizeof(backdoor) + sizeof(grp_reg_map) pdb->vparm1offset = sizeof(backdoor) pdb->vparma1size = sizeof(grp_reg_map) note: if the image will be kept in local memory, no call to the hpi is performed; otherwise, ndismovememory(pdb->parm1offset, ®_local_image(device_id), pdb-vparm1size); aa call the hpi . 2.5 api_t1e1readregistermap() description this function calls the hpi t1/e1 to provide the t1/e1 register map. synopsis status api_t1e1readregistermap ( devaddr deviceaddr void * ) input parameters deviceaddr?specifies the device?s base address as seen by the mpu. output parameters deviceid? identifier used in subsequent device hpi primitives. body call the adequate hpi. returns success err_code pbd->parm1 = port_number (group number) pbd->reqcode = backdoor _read pbd->reqsubcode= backdor_read_xxxx_regiter_map pbd->needsize=sizeof(backdoor) + sizeof(grp_reg_map) pdb-totolsize = sizeof(backdoor) + sizeof(grp_reg_map) pdb->vparm1offset = sizeof(backdoor) pdb->vparma1size = sizeof(bt83xx_device) 2.5.1 api_t1e1configuration() description this function calls the specific device drive api in order to pro- preliminary review 8/16/99 1600
n8478ug1a 2.0 installation evaluation module user?s guide 2.5 api_t1e1readregistermap() n8478ug1a conexant 2-9 preliminary information/conexant proprietary and confidential vide the device driver configuration.. synopsis status api_t1e1configuration ( devaddrdeviceaddr void * ) input parameters deviceaddr?this value specifies the device?s base address as seen by the mpu. output parameters deviceid ?the device identifier used in subsequent device hpi primitives. body: call the adequate hpi returns success example: call t1/e1 hpi to provide the configuration. 2.5.2 api_readdevicestatistics 2.5.3 api_read_device_register() description this function calls the specific device drive api in order to pro- vide the device driver configuration.. synopsis status api_t1e1configuration ( devaddrdeviceaddr void * ) input parameters deviceaddr?specifies the device?s base address as seen by the mpu. output parameters deviceid ? the device identifier used in subsequent device hpi primitives. body: call the adequate hpi returns success example: call t1/e1 hpi to provide the configuration. init backdoor_adapter_init preliminary review 8/16/99 1600
2.0 installation n8478ug1a 2.5 api_t1e1readregistermap() evaluation module user?s guide 2-10 conexant n8478ug1a preliminary information/conexant proprietary and confidential init_device_specific_mode(e1,t1) init_device_diagnostics action_start start_hdlc_loopback reset_global reset_local start_tx_pulse_template start_loopback_option start_tx_isolated_pulse start_tx_all_ones action_stop stop_hdlc_loopback stop_tx_pulse_template stop_loopback_option stop_tx_isolated_pulse stop_tx_all_ones action_configure configure_device configure_hdlc_loopback action_write write_device_register write_shared_memory_location genereal api_readpciconfiguration api_readsharedmemory api_readregistryconfiguration t1e1initdev() description this function initializes a device?s registers to an initial, default state as specified by the t1e1 register configuration structure. all registers configured by other hpi primitives will be overwritten. this function is typically called only once, immediately after t1e1registerdev(). synopsis status t1e1initdev ( preliminary review 8/16/99 1600
n8478ug1a 2.0 installation evaluation module user?s guide 2.5 api_t1e1readregistermap() n8478ug1a conexant 2-11 preliminary information/conexant proprietary and confidential deviddeviceid tregisterconfigstruct*pregisterconfig ) input parameters deviceid ? the device identifier. *pregisterconfig ? pointer to a device configuration structure. this structure contains values for all of the device?s configura- tion and control registers. registers not included are those which are updated by the device. output parameters none returns success error hdlc hal the hal will inculde services such as read and write for the ebus. read_ebus (); write_ebus(); interrupt handler interrupt handler per device preliminary review 8/16/99 1600
2.0 installation n8478ug1a 2.5 api_t1e1readregistermap() evaluation module user?s guide 2-12 conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a conexant 3-1 preliminary information/conexant proprietary and confidential 3 3.0 hardware description 3.1 block diagram figure 3-1 illustrates a block diagram of the evaluation board. it includes four bt8370 circuits, receive and transmit connected (t1 or e1) lines interface, a serial bus used to transfer data between these circuits, and the bt8474 (musycc). the data is transferred between the bt8474 and the host through the peripheral component interconnect (pci) bus. the bt8370 circuits are configured and controlled using the expansion bus (ebus). figure 3-1. bt8474 block diagram 8478_053 bt8370 port 0 bt8370 port 1 bt8370 port 2 bt8370 port 3 address decode logic pci bus serial ports (data) ebus (control) preliminary review 8/16/99 1600
3.0 hardware description n8478ug1a 3.2 expansion bus evaluation module user?s guide 3-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential 3.2 expansion bus the expansion bus, mastered by the bt8474, controls and configures the four bt8370 chips. it is configured as an intel-style bus (refer to the bt8474 datasheet for details), and uses only the sixteen lower address/data lines of the 32 bits available on the bt8474. however, even though 16-bit data transfer can be achieved in this configuration, all ebus data access will be 8 bits wide because the connected devices (the four bt8370 chips and the latch register) support only this format. the address decoding logic is centered on u2 and u3, which generate all necessary chip select signals for the different devices connected to the bus. figure 3-2 illustrates the resulting memory map of the e-bus. figure 3-2. expansion bus memory map 8478_054 bt8370 port 3 bt8370 port 2 bt8370 port 1 bt8370 port 0 write operation ead [31:0] ffff d1ff d000 c1ff c000 b1ff b000 a000 81ff 8000 afff 0000 offset (1) (2) (2) 3. (1) 34000 30000 2c000 28000 20000 all address values in hex. note(s) all values are phsical addresses as they appear on the bus. latch (1) pci physical address location bar1 offset where bar1 pci configuration register 4 (addr 0x10) preliminary review 8/16/99 1600
n8478ug1a 3.0 hardware description evaluation module user?s guide 3.3 pci bus n8478ug1a conexant 3-3 preliminary information/conexant proprietary and confidential the latch (u4) controls some hardware signals on the board. although the latch address ranges from a000 to afff (hex), only one physical location can be accessed with any of these. this latch cannot be read, and only the following bits are used (numbering from 0?7): bit 1?when reset, disables interrupt a on the bt8474 (inta# line disconnected from pci bus). bit 2?when reset, disables interrupt b on the bt8474. bit 4?when reset, activates the reset signal on all four bt8370 devices. this allows the software driver to perform a hardware reset whenever necessary. upon power?up, all these signals are reset (all active); therefore, all bt8370 circuits will remain in the reset state until the software sets bit 4. 3.3 pci bus the pci interface on the bt8474 is connected to a 5 v, 32-bit pci bus. the two interrupt lines, inta* and intb*, can be disabled by software, if necessary, by setting to zero the appropriate bits in the previously described latch. the jtag port is also wired to the connector for testing. the optional j2 header allows connection to the gnt# signal if a pci bus analyzer is used. preliminary review 8/16/99 1600
3.0 hardware description n8478ug1a 3.4 serial buses evaluation module user?s guide 3-4 conexant n8478ug1a preliminary information/conexant proprietary and confidential 3.4 serial buses the bt8474 transfers data to and from the four bt8370 chips, using four independent serial buses. figure 3-3 illustrates all signals used and their direction. figure 3-3. serial bus between musycc and t1 transceivers 8478_055 8474 musycc 8370 port 0 bclk0 - bit clock tfsync0 - tx sync rfsync0 -rx sync roof0 - out of frame td0 - tx data rd0 - rx data bclk1 - bit clock tfsync1 -tx sync rfsync1 -rx sync roof1 - out of frame td1 - tx data rd1 - rx data bclk2 - bit clock tfsync2 -tx sync rfsync2 -rx sync roof2 - out of frame td2 - tx data rd2 - rx data bclk3 - bit clock tfsync3 -tx sync rfsync3 -rx sync roof3 - out of frame td3 - tx data rd3 - rx data 8370 port 1 8370 port 2 8370 port 3 preliminary review 8/16/99 1600
n8478ug1a 3.0 hardware description evaluation module user?s guide 3.5 t1 / e1 line interface n8478ug1a conexant 3-5 preliminary information/conexant proprietary and confidential 3.5 t1 / e1 line interface the line interface connects the bt8370 to the t1 or e1 line. the transformer has a 3 kv insulation to allow the board to pass tests in european countries. the line filter reduces the electromagnetic interference. the polyswitch and p1553ab components (fsx and zx) protect the transformer from power surges. the optional e1 jumper allows the user to change the receive termination impedance to match the t1 or e1 requirements. by default, the board does not have this header and is configured for t1 line (100 ? ). if the jumper is set, the board is configured for e1 (75 ? ). 3.6 bt8370 clocking options the bt8370 offers several synchronization options for its serial port, allowing a flexible clocking configuration. figure 3-4 illustrates the clock inputs and outputs wiring. see the bt8370 data sheet for a description of the different pins and how to use them. figure 3-4. bt8370 serial clock generation 8478 056 (1) common to all 8370 devices. bt8370 10 mhz osc. refclk (1) (1) (1) external clock tcko tsbcki (3-state) rcko cladi shared clock optional shunt to bt8474 clock input clado tcki note(s) preliminary review 8/16/99 1600
3.0 hardware description n8478ug1a 3.6 bt8370 clocking options evaluation module user?s guide 3-6 conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a conexant 4-1 preliminary information/conexant proprietary and confidential 4cn8478 4.0 software architecture 4.1 software block diagram figure 4-1 illustrates the basic software blocks in the cn8478 evm. figure 4-1. software block diagram 8478_057 bt8474 driver user mode kernel mode bt8370 driver devspecific oid_rss_dev_specific driverentry - queryinformationhdlr apis the backdoor mechanism nt ndis?interface application level logical level physical level evm toolbox device io control preliminary review 8/16/99 1600
4.0 software architecture n8478ug1a 4.1 software block diagram evaluation module user?s guide 4-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential communication between the user and kernel modes uses the deviceiocontrol function that passes the defined i/o control code to the ndis driver, requesting the device specific driver. 4.1.1 nt ndis interface the nt ndis interface implements the functions required to comply with the ndis 4.0 specification. these functions respond to query and set operations from the ndis wrapper, and maintain proper state information for the wan links. in the nt kernel mode driver, the starting point is the driverentry function, which initializes driver data structures and prepares the environment for all other components. the query informationhdlr function returns information about the capabilities and status of the driver, in this case, for a specific nic driver handled by the cn8478 evm toolbox. this function calls the devspecific function, which is the envelope for all apis used to configure and perform the application requests. 4.1.2 cn8478 driver the cn8478 driver is the set of functions used to reset, configure, and maintain the device. the cn8478 driver supports a dynamically grouped configuration: channel assignments protocols (transparent, ss7-hdlc-fcs16, hdlc-fcs16, hdlc-fcs32) receive and transmit message loopbacks time slot assignments communication between the cn8478 and the host is done through the service request mechanism. the following service requests are supported by the cn8478 driver: soft chip reset global configuration channel group configuration read channel configuration channel activation and deactivation the device must acknowledge each request to a specific group before any other service request may be issued. all buffer descriptors and packet blocks are statically allocated; however, a large amount of ram is required. the transmit and receive mechanism is implemented by a linked circular list. the host creates a circular list of buffers for each channel, and the last buffer in the list points to the first one. all buffers in the list are initially host-owned. the host-fill process merely checks the owner status of the next buffer before filling. if the next buffer is host-owned, the host fills it and flips the owner bit to grant ownership to musycc. if the next buffer is musycc-owned, the host waits for musycc to empty the buffer and become host-owned. at this point, the buffer can be filled. preliminary review 8/16/99 1600
m8478ug1a 4.0 software architecture evaluation module user?s guide 4.2 development tools n8478ug1a conexant 4-3 preliminary information/conexant proprietary and confidential 4.1.3 bt8370 driver the bt8370 driver is the set of functions used to reset, configure, and maintain the device. background threads monitor the current state of the device to correct any deviation from the expected performance level. 4.2 development tools the development tools are microsoft visual c++, professional edition; microsoft visual basic, professional edition; and microsoft development network?ddk. preliminary review 8/16/99 1600
4.0 software architecture n8478ug1a 4.3 apis?backdoor mechanism evaluation module user?s guide 4-4 conexant n8478ug1a preliminary information/conexant proprietary and confidential 4.3 apis?backdoor mechanism you can interface with the software driver by using the backdoor structure, submitting requests and receiving responses. this interface is called apis?backdoor mechanism. figure 4-2 illustrates the backdoor mechanism. tables 4-1 through 4-21 list the backdoor parameters, instances, and hex values. figure 4-2. backdoor mechanism 8478_058 vparam1size vparam1offset vparam2size vparam2offset data 1 data 2 preliminary review 8/16/99 1600
m8478ug1a 4.0 software architecture evaluation module user?s guide 4.3 apis?backdoor mechanism n8478ug1a conexant 4-5 preliminary information/conexant proprietary and confidential 4.3.1 backdoor read table 4-1. read shared memory map backdoor parameters instances keycode rok reqcode backdoor_read reqsubcode backdoor_read_shared_mem param1 group number vparam1size shared memory map size vparam1offset size of (backdoor structure) note(s): all cn8478 shared memory map values are returned in the data 1 area. table 4-2. read shared memory map backdoor parameters instances keycode rok reqcode backdoor_read reqsubcode backdoor_read_shared_mem_location param1 group number param2 regoffset + current channel number (if required) note(s): the output of the register content in shared memory is returned in param 3. table 4-3. read shared memory map backdoor parameters instances keycode rok reqcode backdoor_read reqsubcode backdoor_read_bt847x_register_map param1 group number vparam1size shared memory map size vparam1offset sizeof(backdoor structure) note(s): all register map values are returned in the data1 area. preliminary review 8/16/99 1600
4.0 software architecture n8478ug1a 4.3 apis?backdoor mechanism evaluation module user?s guide 4-6 conexant n8478ug1a preliminary information/conexant proprietary and confidential . table 4-4. read bt847x register backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_read 0 reqsubcode backdoor_read_bt847x_register 3 param1 group number 0...3 param2 regoffset + currentchannelnumber (if required) 0...800 note(s): the wan miniport driver returns register value in param3. table 4-5. read bt847x register backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_read 0 reqsubcode backdoor_read_bt847x_register 3 param1 group number 0...3 param2 regoffset + currentchannelnumber (if required) 0...800 keycode rok 524f4b00 note(s): all bt8370 registers values are returned in the data 1 area. table 4-6. read bt8370 register backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_read 0 reqsubcode backdoor_read_bt8370_register 7 param1 group number 0...3 param2 regoffset + currentchannelnumber (if required) 0...1ff note(s): the wan miniport driver returns register value in param3. preliminary review 8/16/99 1600
m8478ug1a 4.0 software architecture evaluation module user?s guide 4.3 apis?backdoor mechanism n8478ug1a conexant 4-7 preliminary information/conexant proprietary and confidential . table 4-7. read bt8370 register backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_read 0 reqsubcode backdoor_read_bt8370_register 7 param1 group number 0...3 param2 regoffset + currentchannelnumber (if required) 0...1ff keycode rok 524f4b00 note(s): the wan miniport driver returns register value in param3. table 4-8. read message maps backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_read 0 reqsubcode backdoor_read_message_maps 9 param1 group number 0...3 vparam1size msg_desc tx_messages_per_ch num_channels_per_group 3 2 20 = c0 (192 dec) vparam1offset size of (backdoor structure) 54 vparam2size msg_desc rx_messages_per_ch num_channels_per_group 3 8 20 = 300h (768 dec) vparam2offset size of (backdoor structure) + vparam1size note(s): 1. tx_messages_per_ch is returned in param2. 2. tx_message_length is returned in param3. 3. rx_messages_per_ch is returned in param4. 4. rx_message_length is returned in param5. 5. all message descriptors (buffer descriptor, data pointer, and pointer to next message descriptor) for each channel for transmitted messages are returned in the data1 area. 6. all message descriptors (buffer descriptor, data pointer, and pointer to next message descriptor) for each channel for received messages are returned in the data2 area. preliminary review 8/16/99 1600
4.0 software architecture n8478ug1a 4.3 apis?backdoor mechanism evaluation module user?s guide 4-8 conexant n8478ug1a preliminary information/conexant proprietary and confidential figure 4-3 illustrates the structure of data in shared memory. there are two transmit messages per channel, and the transmit message length is equal to 2 kb. figure 4-3. structure of data in shared memory 8478_067 description data ptr next ptr description data ptr next ptr 2 kb data 2 kb data table 4-9. read message data backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_read 0 reqsubcode backdoor_read_message_data 10 param1 group number 0...3 param2 channel number 0...1f param3 transmit message number 0 or 1 param4 receive message number 0..7 vparam1size tx_messages_length 800 (2048 dec) vparam1offset size of (backdoor structure) 54 vparam2size rx_messages_length 800 (2048 dec) vparam2offset size of (backdoor structure) + vparam1size 854 note(s): 1. tx message data is returned in the data1 area. 2. rx message data is returned in the data2 area. preliminary review 8/16/99 1600
m8478ug1a 4.0 software architecture evaluation module user?s guide 4.3 apis?backdoor mechanism n8478ug1a conexant 4-9 preliminary information/conexant proprietary and confidential table 4-10. read pci configuration backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_read 0 reqsubcode backdoor_read_pci_config 11 vparam1size ? 0c vparam1offset size of (backdoor structure) 54 vparam2size ? 0c vparam2offset size of (backdoor structure) + vparam1size 60 note(s): function 0 pci configuration is returned in the data1 area. table 0-1. read registry configuration backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_read 0 reqsubcode backdoor_read_registery_config 12 vparam1size common_parameters + (group_parameters num_of_group) 8 + (10 4) = 40h (64 dec) vparam1offset size of (backdoor structure) 54h vparam2size max_groups num_channels_per_group max_called_number_length 4 20 28 = 1400h (5120 dec) vparam2offset size of (backdoor structure) + vparam1size 94h note(s): the registry configuration parameters are returned in the data1 area. preliminary review 8/16/99 1600
4.0 software architecture n8478ug1a 4.3 apis?backdoor mechanism evaluation module user?s guide 4-10 conexant n8478ug1a preliminary information/conexant proprietary and confidential 4.3.2 backdoor write table 4-11. write bt8370 register backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_write 5 reqsubcode backdoor_write_bt8370_register 0 param1 group number 0...3 param2 regoffset + current channel number (if required) 0...1ff table 4-12. write bt847x register backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_write 5 reqsubcode backdoor_write_bt847x_register 1 param1 group number 0...3 param2 regoffset + current channel number (if required) 0...800 table 4-13. write bt847x register map backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_write 5 reqsubcode backdoor_write_shared_mem_location 2 param1 group number 0...3 param2 regoffset + current channel number (if required) 0...800 preliminary review 8/16/99 1600
m8478ug1a 4.0 software architecture evaluation module user?s guide 4.3 apis?backdoor mechanism n8478ug1a conexant 4-11 preliminary information/conexant proprietary and confidential 4.3.3 backdoor initialization 4.3.4 backdoor action start table 4-14. card initialization backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_init 1 reqsubcode backdoor_init_adapter 0 table 4-15. bt847x initialization backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_init 1 reqsubcode backdoor_init_bt847x 1 table 4-16. bt847x loopback without self test backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_action_start 2 reqsubcode backdoor_action_start_bt847x_ loopback 0 param1 group number 0...3 param2 channel number 0...1f table 0-2. bt847x loopback with self test backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_action_start 2 reqsubcode backdoor_action_start_bt847x_ loopbacktest 1 param1 group number 0...3 param2 channel number 0...1f preliminary review 8/16/99 1600
4.0 software architecture n8478ug1a 4.3 apis?backdoor mechanism evaluation module user?s guide 4-12 conexant n8478ug1a preliminary information/conexant proprietary and confidential 4.3.5 backdoor action stop table 4-17. stop bt847x loopback test backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_action_stop 3 reqsubcode backdoor_action_stop_bt847x_ loopback 0 param1 group number 0...3 param2 channel number or ffffffffh (for all channels) 0...1f preliminary review 8/16/99 1600
m8478ug1a 4.0 software architecture evaluation module user?s guide 4.3 apis?backdoor mechanism n8478ug1a conexant 4-13 preliminary information/conexant proprietary and confidential 4.3.6 backdoor action configuration table 4-18. configuration of bt847x time slot assignments and channel protocols backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_action_configure 4 reqsubcode backdoor_action_configure_bt847x 4 param1 group number 0...3 vparam1size max number of time slots number of groups 80h 4 = 200h (512) vparam1offset size of (backdoor structure) 54h vparam2size (not used) 100h 4 = 400h (1024) vparam2offset size of (backdoor structure) + vparam1size 54h +200h = 254h vparam3size number of channels per group number of groups 20h 4 = 80h (128) vparam3offset size of (backdoor structure) + vparam1size + vparam2size 54h +200h + 400h = 654h data 1 data1[0] = channel assigned to time slot 0 data1[1] = channel assigned to time slot 1 ? data1[127] = channel assigned to time slot 127 0...1f 0..1f ... 0...1f data2 (not used) ? data3 data3[0] = protocol assigned to channel 0 data3[1] = protocol assigned to channel 1 ? data3[31] = protocol assigned to channel 31 0...3 0...3 .. 0...3 preliminary review 8/16/99 1600
4.0 software architecture n8478ug1a 4.3 apis?backdoor mechanism evaluation module user?s guide 4-14 conexant n8478ug1a preliminary information/conexant proprietary and confidential 4.3.7 backdoor loop table 4-19. configure loopback message backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_action_configure 4 reqsubcode backdoor_action_configure_loopbackmessage 9 param1 loopback message 0?quick brown fox 1?0x00 pattern 2?0x55 pattern 3?0xaa pattern 4?0xff pattern 5?user define pattern 0...5 param2 (optional) user define pattern value 0...ff table 4-20. run bt8370 loopback backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_loop 6 reqsubcode backdoor_loop_run 2 param1 group number 0...3 param2 0 or channel number for local or remote loop per channel 0 or 0...1f param3 loopback type: 2?framer_loopback 3?perchannel_local_loopback 4?perchannel_remote_loopback 2...4 table 4-21. stop bt8370 loopback backdoor parameters instances hex value keycode rok 524f4b00 reqcode backdoor_loop 6 reqsubcode backdoor_loop_stop 2 param1 group number 0...3 param2 0 or channel number for local or remote loop per channel 0 or 0...1f param3 loopback type: 2?framer_loopback 3?perchannel_local_loopback 4?perchannel_remote_loopback 2...4 preliminary review 8/16/99 1600
n8478ug1a conexant 5-1 preliminary information/conexant proprietary and confidential 5 5.0 using the cn8478 evm toolbox this chapter describes how to use the cn8478 evm toolbox for windows nt. 5.1 starting the cn8478 evm toolbox the software installation process adds the cn8478 evm toolbox to the programs menu. to start the cn8478 evm toolbox, perform these steps: 1. from the start menu, choose programs. 2. from the program menu, click on cn8478 evm toolbox. the main menu appears, as illustrated in figure 5-1 . the main menu is always displayed so you can move from one level to another. all windows can be open at the same time. 5.2 main menu the cn8478 evm can be configured at three levels: 1. application level?performs testing and maintenance. 2. logical level?allows channel assignments and time slot monitoring. 3. physical level?is a component register editor. figure 5-1. main menu of the cn8478 evm toolbox preliminary review 8/16/99 1600
5.0 using the cn8478 evm toolbox n8478ug1a 5.3 application level evaluation module user?s guide 5-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential 5.3 application level use the application level to perform tests and maintenance. the application level window illustrated in figure 5-2 is used to run loopback tests, analyze statistics, view received and transmitted messages, examine the pci bus configuration, and update registers. the cn8478 is initialized each time the application level is opened. therefore, open it first and leave it open while working in other levels. 5.3.1 application level menus the enabled menus are file, options, and help. edit is not enabled. 5.3.1.1 file menu you can dump either cn8478 registers or bt8370 registers by saving to a file and folder you select. the address and contents of the device?s registers are saved in the file. the file can be retrieved through notepad, word, or another windows nt program. figure 5-2. application level window preliminary review 8/16/99 1600
n8478ug1a 5.0 using the cn8478 evm toolbox evaluation module user?s guide 5.3 application level n8478ug1a conexant 5-3 preliminary information/conexant proprietary and confidential 5.3.1.2 options menu use the options menu (illustrated in figure 5-3 ) to initialize the card and the cn8478, select loopback message patterns, explore messages, view card configuration, and view the pci configuration. initialize card and initialize cn8478 initialize card and initialize cn8478 are like reset buttons. initialize card performs a full reset (cn8478 and bt8370). initialize cn8478 resets only the cn8478. loopback messages type the loopback message type option allows you to select the pattern of the message type. six patterns are available (quick brown fox, 0x00 pattern, 0x55 pattern, 0xaa pattern, 0xff pattern, and user defined). explore messages if you select the explore messages option during a loopback test, the message descriptor and message data are displayed for the active channel, as illustrated in figure 5-4 . figure 5-3. options menu preliminary review 8/16/99 1600
5.0 using the cn8478 evm toolbox n8478ug1a 5.3 application level evaluation module user?s guide 5-4 conexant n8478ug1a preliminary information/conexant proprietary and confidential figure 5-4. explore messages window note(s): message data can be displayed in either hexadecimal or ascii format, as illustrated above. double-click the message data to switch between formats. preliminary review 8/16/99 1600
n8478ug1a 5.0 using the cn8478 evm toolbox evaluation module user?s guide 5.3 application level n8478ug1a conexant 5-5 preliminary information/conexant proprietary and confidential view pci configuration the pci configuration window displays the pci configuration parameters, as illustrated in figure 5-5 . 5.3.1.3 help menu online help is accessible from the help button in the application level window. help includes information about the cn8478 evm toolbox and the cn8478 and bt8370 chips. choices include: a brief version of this chapter cn8478/cn8474a/cn8472a/cn8471a data sheet access to conexant?s home page 5.3.2 loopback tests the application level window provides a framer loopback test for diagnostics, maintenance, and troubleshooting. there are two loopback interfaces, one for each device?the bt8370 and the cn8478. 5.3.2.1 bt8370 loopback select the applicable bt8370 device and port by selecting the group from the group drop-down list box. the default configuration for bt8370 loopback is run (the arrow is green). clicking the stop button stops the loopback (the arrow turns red). the stop condition takes the bt8370 out of loopback mode but does not stop the transmit message if a cn8478 loopback test is still running. the bt8370 loopback interface is illustrated in figure 5-6 . figure 5-5. pci configuration window preliminary review 8/16/99 1600
5.0 using the cn8478 evm toolbox n8478ug1a 5.3 application level evaluation module user?s guide 5-6 conexant n8478ug1a preliminary information/conexant proprietary and confidential 5.3.2.2 cn8478 loopback while the bt8370 is running, you can run a cn8478 loopback test. the cn8478 default configuration is one time slot per channel, protocol hdlc-fcs16. (use the logical level to change the configurations.) to run a loopback test, follow these steps: 1. select the group (port) number from the group drop-down list box in the loopback tests area, illustrated in figure 5-7 . 2. if you want to disable self test for a particular channel, it must be done before you begin the test. select the channel from the channel drop-down list box, and click with self test to remove the check. when self test is disabled, matching between transmit and receive is not performed for that channel during the loopback test. 3. in the grid at the bottom of the application level window, select the channels you want to test by clicking at the junction of the channel to test and the run bt847x test row. this begins the test. an example of the run cn8478 test running 10 of the 23 channels is illustrated in figure 5-8 . 4. with self test enabled, the verify success box indicates whether or not the contents of the transmitted frame are identical with the contents of the received frame; the matching is done byte by byte. in figure 5-8 , all channels have self test enabled except channel 6. 5. to stop the loopback test in one channel, click the x under the channel number. figure 5-6. bt8370 loopback test area figure 5-7. cn8478 loopback tests area preliminary review 8/16/99 1600
n8478ug1a 5.0 using the cn8478 evm toolbox evaluation module user?s guide 5.3 application level n8478ug1a conexant 5-7 preliminary information/conexant proprietary and confidential during the loopback test you have four options (in addition to those on the options menu): stop tests for all channels show statistics monitor errors view transmit and receive information rate stop test when you click stop test for all channels, all loopback tests stop. click again in the grid to restart the tests individually. show statistics when you click show statistics, the channel statistics window appears, which displays statistics of transmit and receive messages, as well as important events and errors for the selected channel. you can also double-click anywhere in the grid during the loopback test to show statistics. figure 5-9 illustrates the statistics for channel 4. figure 5-8. example of test note(s): a gray column means that the corresponding channel is disabled. in t1 interface mode, the channels 24 through 31 are disabled. figure 5-9. channel statistics window preliminary review 8/16/99 1600
5.0 using the cn8478 evm toolbox n8478ug1a 5.3 application level evaluation module user?s guide 5-8 conexant n8478ug1a preliminary information/conexant proprietary and confidential monitor errors when you click monitor errors, the toolbox retrieves real-time information from the driver related to receive and transmit errors in all running channels. the display is updated every five seconds. receive errors are checksum, buffers, abort, short, and out-of-frame. transmit errors are abort and short. another error is verify failed. when you click stop monitoring, the grid returns to the loopback, which has continued running in the background. figure 5-10 illustrates the monitor errors display. transmit and receive information the transmit and receive information area, illustrated in figure 5-11 , gives information about the number of bytes received and transmitted and the data rate in bits-per-second for the active channels. when a test is running, transmit and receive information is updated each second. figure 5-10. monitor errors display figure 5-11. transmit and receive information area preliminary review 8/16/99 1600
n8478ug1a 5.0 using the cn8478 evm toolbox evaluation module user?s guide 5.3 application level n8478ug1a conexant 5-9 preliminary information/conexant proprietary and confidential 5.3.3 summary of application level user interactions in the application window are listed in table 5-1 . table 5-1. summary of application level window name description file dumps bt8487 registers or bt8370 registers into a file. options initialize card?initialize the adapter. initialize cn8478?initialize the cn8478. loopback message type?loopback messages type for testing cn8478. explore messages?zoom the messages (ascii and hex) of the specific channel. view configuration parameters?view the registry configuration parameters. view pci configuration?view pci configuration. help help file online. group specifies the number of the bt8370 devices used in the cn8478 evm board. bt8370 loopback stops or runs the bt8370 loopback. self test compares the content of the tx and rx messages during loopback tests. run cn8478 test starts the cn8478 loopback test for each channel selected. stop test for all ch stops the cn8478 loopback test for all the channels. show statistics shows statistics for the group and channel selected. min and max displays minimum and maximum number of channels that can be tested. tx bytes out/rx bytes in displays tx and rx information about transmission speed. monitor errors checks for rx and tx errors. preliminary review 8/16/99 1600
5.0 using the cn8478 evm toolbox n8478ug1a 5.4 logical level evaluation module user?s guide 5-10 conexant n8478ug1a preliminary information/conexant proprietary and confidential 5.4 logical level in logical level, you can configure the protocol and time slots? assignment for each logical channel. note: the configuration should not be changed while the channels are active. this means that a ?stop test for all ch? is recommended before changing channel configurations. the cn8478 is initialized when the application level is opened. therefore, open it and leave it open while working in the logical level. there are two modes in logical level: cn8478 and bt8370. 5.4.1 cn8478 logical level the timeslot map configuration area allows hyperchannel capability tests. you can map several time slots on one logical channel and then run a loopback test in the application level window. figure 5-12 illustrates the logical level window. the speed of appropriate channels is shown in the transmit and receive information area. follow these steps to assign a new time slot to a channel: 1. select the group in the options menu. 2. in the bt847x logical level window, click the specific channel, then click the time slot. the color of the time slot cell changes to match the channel cell color. 3. when you finish selecting time slots for the channel, click the write button to save the configuration. (clicking default causes the configuration to return to one time slot per channel.) follow these steps to assign protocols to a channel: 1. click one of the four protocols in the protocol area, and then click the channel. figure 5-12. bt847x logical level window preliminary review 8/16/99 1600
n8478ug1a 5.0 using the cn8478 evm toolbox evaluation module user?s guide 5.4 logical level n8478ug1a conexant 5-11 preliminary information/conexant proprietary and confidential 2. click the write button to save the desired configuration in the 8474 register map. 5.4.2 bt8370 logical level the bt8370 logical level window, illustrated in figure 5-13 , displays information about all bt8370 registers on each channel. in this window, the refresh button updates the register value. preliminary review 8/16/99 1600
5.0 using the cn8478 evm toolbox n8478ug1a 5.4 logical level evaluation module user?s guide 5-12 conexant n8478ug1a preliminary information/conexant proprietary and confidential 5.4.3 summaries of logical level windows table 5-2 and table 5-3 lists user interactions in the cn8478 and bt8370 logical level window respectively. figure 5-13. bt8370 logical level window table 5-2. summary of cn8478 logical level window name description file exit devices bt8370 and cn8478 options refresh?refreshes the screen. group?specifies the 8370 device to be used loopback message type?displays types of loopback messages view configuration parameter?displays the registry configuration parameters view pci configuration?displays the pci configuration help online help time map configuration time slots assignments for each logical channel protocol configuration protocol configuration per channel default returns to default configuration?one time slot per channel, protocol hdlc-fcs16 write write user?s configuration preliminary review 8/16/99 1600
n8478ug1a 5.0 using the cn8478 evm toolbox evaluation module user?s guide 5.4 logical level n8478ug1a conexant 5-13 preliminary information/conexant proprietary and confidential table 5-3. summary of bt8370 logical level window name description file exit devices bt8370 / cn8478 help online help group specifies the number of the bt8370 devices used in the cn8478 evm board register drop-down menu of registers refresh provides latest register value preliminary review 8/16/99 1600
5.0 using the cn8478 evm toolbox n8478ug1a 5.5 physical level evaluation module user?s guide 5-14 conexant n8478ug1a preliminary information/conexant proprietary and confidential 5.5 physical level the physical level is a component register editor where you configure your settings. the default is the cn8478 registers window, where you can edit the cn8478 and bt8472 devices. you can select the bt8370 registers window from the devices menu. the cn8478 is initialized when the application level is opened. therefore, open it and leave it open while working in the physical level. 5.5.1 register area each register consists of an address, a name, and list of fields. each field consists of a name, an option list or a range of values, and description. select the group and channel before selecting the register. figure 5-14 illustrates the cn8478 registers window. 5.5.2 source, values, and destination area select where the value is to be read or written in the source and destination areas. on the cn8478, some registers are present both in shared memory and in the register map. 5.5.2.1 read all registers are read at the opening of the window or during a device selection. to update the register value, click the read button. 5.5.2.2 write when you configure something differently from the default configuration, you must click the write button. the data can be written into either shared memory or the register map. figure 5-14. cn8478 registers window preliminary review 8/16/99 1600
n8478ug1a 5.0 using the cn8478 evm toolbox evaluation module user?s guide 5.5 physical level n8478ug1a conexant 5-15 preliminary information/conexant proprietary and confidential 5.5.2.3 values in the values area, the contents of a specific register are displayed in three different formats: current, shared memory, and register map. current in the current box, you can enter a specific value for a specific register that can be written in either shared memory or the register map. an automatic check is done that allows you to write to specific registers in the register map area. shared memory this field displays the variable?s content from the shared memory. register map this field displays the variable?s content from the register map. 5.5.2.4 description bar the description bar at the bottom of the screen describes the selected bit field. 5.5.3 summary of physical level table 5-4 lists the user interactions with the registers windows. table 5-4. summary of registers window interactions name description file dump?dumps the registers into a file exit edit cut, copy, paste, delete devices cn8478 or bt8370 options refresh help online help grp (group) specifies the group (port) from 0 ? 3 ch (channel) specifies the channel from 0 ? 31 register specifies registers mapped in either shared memory or register map field specifies the bit field map related to the register map options/value(hex)/ranges specifies values and ranges for the register map source and destination read or write to shared memory or register map in these fields values displays a register?s contents current/shared memory/register map displays component contents of register of the selected bit field mask in shared memory or register map description bar displays the description of the current bit field preliminary review 8/16/99 1600
5.0 using the cn8478 evm toolbox n8478ug1a 5.5 physical level evaluation module user?s guide 5-16 conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a conexant 6-1 preliminary information/conexant proprietary and confidential 6 6.0 list of acronyms and abbreviations api application program interface ebus expansion bus hdlc high-level data link control inta integer array jtag test access port and boundary scan architecture ndis network driver interface specification nic network interface controller pci peripheral component interconnect pdf portable document format preliminary review 8/16/99 1600
6.0 list of acronyms and abbreviations n8478ug1a evaluation module user?s guide 6-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a conexant a-1 preliminary information/conexant proprietary and confidential a appendix a: sample connection the typical development environment illustrated in figure a-1 consists of a host computer, a pci bus, version 2.0 or higher, and cn8478 evm software. the evaluation environment consists of three types of system components: performance test (which contains the network simulator), target test, and protocol analyzer. figure a-1. typical development environment 8478_059 8474evm card typical environment host computer ? ibm pc or compatible 8474evm software network simulator performance test target - diagnostics - integration protocol analyzer t1/e1 analyzer evaluation preliminary review 8/16/99 1600
appendix a : sample connection n8478ug1a evaluation module user?s guide a-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a conexant b-1 preliminary information/conexant proprietary and confidential b appendix b: bill of materials table b-1 displays the bill of materials. figure b-1. bill of materials (1 of 3) ite m qty reference value type manufacturer body rss part # 1 51 c1, c2, c3, c4, c6, c7, c8, c9, c10, c11, c12, c13, c14, c15, c16, c17, c18, c19, c20, c22, c23, c24, c25, c26, c27, c28, c32, c33, c34, c35, c36, c37, c38, c42, c43, c44, c45, c46, c47, c48, c52, c53, c54, c55, c56, c57, c58, c62, c63, c64, c65 0.1 20% 50 v 0805 5404r20-031 25 c5, c21, c31, c41, c51 10 20% 6 v avx smt 12.6x6.3 5402r02-032 34 c29, c39, c49, c59 100 p 5% 50 v 0805 5404r19-025 44 c30, c40, c50, c60 15 p 5% 100 v 0805 5404r19-015 51 c61 (no load) 0.1 20% 50 v 0805 5404r20-031: 616 d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15, d16 6.2 v motorola mmsz5234bt1 74 e1, e2, e3, e4 jumper-2 ca-s36-25b-45 816 fs1, fs2, fs3, fs4, fs5, fs6, fs7, fs8, fs9, fs10, fs11, fs12, fs13, fs14, fs15, fs16 polyswitch raychem tr600-160 91 jp1 pci edge connector 10 1 j1 con2 ca-s36-25b-45 11 1 j2 con1 ca-s36-25b-45 12 4 j3, j4, j5, j6 rj48c 613r51-003 613r51-003 preliminary review 8/16/99 1600
appendix b : bill of materials n8478ug1a document title b-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential 13 4 l1, l2, l3, l4 filter pulse_engineering pe65854 14 3 r1, r5, r8 05% 0.1w 0805 5424r08-146 15 7 r2, r6, r7, r18, r19, r20, r21 100k 5% 0.1w 0805 5424r08-097 16 2 r3, r9 10k 5% 0.1w 0805 5424r08-073 17 1 r4 100 5% 0.1 w 0805 5424r08-025 18 8 r10, r11, r12, r13, r14, r15, r16, r17 47k 5% 0.1w 0805 5424r08-089 19 2 r22, r23 10k 5% 0.1w 0805 5424r08-073 20 4 r24, r30, r36, r42 51.1 1% 0.25w 1206 5424r01-069 21 4 r25, r31, r37, r43 12.4k 1% 0.1w 0805 5424r07-297 22 4 r26, r32, r38, r44 1k 1% 0.25w 1206 5424r01-193 23 4 r27, r33, r39, r45 240 1% 0.25w 1206 5424r01-134 24 8 r46, r47, r48, r49, r50, r51, r52, r53 100 1% 0.25w 1206 5424r01-097 25 4 tr1, tr2, tr3, tr4 t1044 pulse_eng t1044 26 1 u1 bt8474 brooktree pqfp-160pin bt8474 27 1 u2 74f373 ti soic-20pin-dw 74f373-dw 28 1 u3 74f138 ti soic-16pin-d 74f138-d figure b-1. bill of materials (2 of 3) (continued) ite m qty reference value type manufacturer body rss part # preliminary review 8/16/99 1600
n8478ug1a appendix b : bill of materials document title n8478ug1a conexant b-3 preliminary information/conexant proprietary and confidential 29 1 u4 74hct174 soic-16pin-d 74hct174-d 30 1 u5 74f00 soic-14pin-d 74f00-d 31 1 u6 74hct03 soic-14pin-d 74hct03-d 32 4 u7, u8, u9, u10 bt8370 rev d - 80mqfp 33 1 y1 10 mhz osc. fox f3356-10.000 mhz 34 1 zu1 pci_bracket gompf 9334-0006 35 1 zu2 pci_retainer gompf 9100-0000b 36 2 zu3, zu4 screw_bracket 37 2 zu5, zu6 screw_retainer z1, z2, z3, z4, z5, z6, z7, z8 p1553ab teccor mod-to220 p1553ab figure b-1. bill of materials (3 of 3) (continued) ite m qty reference value type manufacturer body rss part # preliminary review 8/16/99 1600
appendix b : bill of materials n8478ug1a document title b-4 conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a conexant c-1 preliminary information/conexant proprietary and confidential c appendix c: mechanical specifications figure c-1. 160-pin pqfp package mechanical drawing 160 mqfp - 1.95/0.33 form top view bottom view d pin 1 e e1 d1 b e a2 a a1 1.95 (.077) ref. l s y m b o l all dimensions in millimeters a a1 a2 d d1 e e1 l e b min. ---- 0.25 3.17 31.65 27.90 31.65 27.90 0.65 0.22 nom. ---- ---- 3.42 31.90 28.00 31.90 28.00 ---- 0.65 bsc. ---- max. 4.07 ---- 3.67 32.15 28.10 32.15 28.10 0.95 0.38 8478_060 preliminary review 8/16/99 1600
appendix c : mechanical specifications n8478ug1a evaluation module user?s guide c-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
n8478ug1a conexant d-1 preliminary information/conexant proprietary and confidential d appendix d: circuit schematics figures d-1 through d-5 illustrate the following: 1. pci interface 2. t1/e1 interface?port 1 3. t1/e1 interface?port 2 4. t1/e1 interface?port 3 5. t1/e1 interface?port 4 preliminary review 8/16/99 1600
appendix d : circuit schematics n8478ug1a evaluation module user?s guide d-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential figure d-1. pci interface pci interface chip select $8xxx --> bt8370 port 1 notes: 1 - all capacitor values are in uf unl ess otherwise specified 2 - all resistor values are in ohms latch reg ister decoupling capacitors for u6 u7 u8 u9 u10 spare gate $axxx --> latch regi ster (write only) r8 not ins talled $bxxx - $dxxx --> bt8370 port 2, 3, 4 external clock input connector interrupt e nable pci bracket, retainer and screws rev. b optional ju mper optional terminating components nimitz4 ~liusel_3 ~wr ~rd ale refclk ~reset eclk ead[0:8] tdat3 rdat3 rfsync3 bclk3 roof3 ~liu_irq tfsync3 shared_clk extclk nimitz2 ~liusel_1 ~wr ~rd ale refclk ~reset eclk ead[0:8] tdat1 rdat1 rfsync1 bclk1 roof1 ~liu_irq tfsync1 shared_clk extclk nimitz3 ~liusel_2 ~wr ~rd ale refclk ~reset eclk ead[0:8] tdat2 rdat2 rfsync2 bclk2 roof2 ~liu_irq tfsync2 extclk shared_clk nimitz1 ~liusel_0 ~wr ~rd ale refclk ~reset eclk ead[0:8] tdat0 rdat0 rfsync0 bclk0 roof0 ~liu_irq tfsync0 extclk shared_clk ~pci_intb ~e_irq ad08 ad07 ad05 ad03 ad01 ad09 ad08 ad07 ad06 ad05 ad04 ad03 ad02 ad01 ad00 ~pci_inta ~mus_intb ~mus_inta bclk0 tfsync0 roof0 bclk0 rfsync0 ~liu_sel0 ad09 ad06 ad04 ad02 ad00 td0 rd0 bclk1 tfsync1 roof1 bclk1 rfsync1 td1 rd1 bclk2 tfsync2 roof2 bclk2 rfsync2 td2 rd2 bclk3 tfsync3 roof3 bclk3 rfsync3 td3 rd3 ~latchsel td1 rd1 roof1 ~e_irq td2 rd2 roof2 ~e_irq td3 rd3 roof3 ~e_irq ~liu_sel1 ~liu_sel2 ~liu_sel3 ~liu_sel3 ~liu_sel2 ~liu_sel1 bclk3 bclk2 bclk1 ~latchsel td0 ~liu_sel0 rd0 roof0 tfsync1 tfsync2 tfsync0 tfsync3 ~e_irq bclk0 a12 ead13 ead4 ead1 rfsync1 ead13 rfsync2 ead0 ead2 ead[0..15] ale rfsync3 ead15 ead12 ead2 ead15 ead7 ead10 ead14 ead1 ~rd a15 ead11 ~wr a14 a12 ead8 a[12..15] ead3 a13 ead4 rfsync0 a15 ead5 ead0 ead5 ead9 ead6 a13 ead3 ead14 a14 ead12 ~wr ad22 ad16 ad26 ad18 ad19 ad17 ad29 ad10 ad[0..31] ad19 ad25 ad28 ad18 ad23 ad31 ad12 ad14 ad21 ad20 ad15 ad24 ad25 ad10 ad27 ad30 ad14 ad24 ad17 ad21 ad13 ad11 ad11 ad30 ad15 ad26 ad12 ad29 ad16 ad13 ad22 ad27 ad20 ad23 ad28 ad31 extclk ~mus_inta ~pci_intb ~pci_inta ~mus_intb ~reset vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc vcc u4 74hct174 d1 3 d2 4 d3 6 d4 11 d5 13 d6 14 clk 9 clr 1 q1 2 q2 5 q3 7 q4 10 q5 12 q6 15 u3 74f138 a 1 b 2 c 3 g1 6 g2a 4 g2b 5 y0 15 y1 14 y2 13 y3 12 y4 11 y5 10 y6 9 y7 7 u2 74f373 d0 3 d1 4 d2 7 d3 8 d4 13 d5 14 d6 17 d7 18 oc 1 g 11 q0 2 q1 5 q2 6 q3 9 q4 12 q5 15 q6 16 q7 19 j2 1 r17 47k r16 47k r15 47k r14 47k r13 47k r12 47k r11 47k r10 47k c14 .1 c4 .1 c16 .1 c5 10 c15 .1 r7 100k r6 100k r2 100k u1 bt8474 vddo 160 vddo 140 vddo 120 vddo 89 vddo 80 vddo 59 vddo 40 vddo 32 vddc 108 vddc 96 vddc 28 vddc 3 vddi 14 vsso 141 vsso 130 vsso 121 vsso 90 vsso 81 vsso 70 vsso 60 vsso 50 vsso 41 vsso 33 vsso 1 vssc 110 vssc 98 vssc 5 vssi 104 vssc 30 nc-reserved 155 hlda (bg*) 154 hold (br*) 153 eint* 152 ale (as*) 151 rd* (ds*) 150 wr* (r/wr*) 149 roof1 12 rclk1 13 rsync1 15 rdat1 16 roof0 17 rclk0 18 rsync0 19 rdat0 20 tck 21 trst* 22 tms 23 tdo 24 tdi 25 intb* 26 inta* 27 pclk 29 prst* 31 gnt* 34 req* 35 idsel 47 frame* 58 irdy* 61 trdy* 62 devsel* 63 stop* 64 serr* 66 perr* 65 par 67 eclk 148 ebe3* 156 ebe2* 157 ebe1* 158 ebe0* 159 ead31 147 ead30 146 ead29 145 ead28 144 ead27 143 ead26 142 ead25 139 ead24 138 ead23 137 ead22 136 ead21 135 ead20 134 ead19 133 ead18 132 ead17 131 ead16 129 ead15 128 ead14 127 ead13 126 ead12 125 ead11 124 ead10 123 ead9 122 ead8 119 ead7 118 ead6 117 ead5 116 ead4 115 ead3 114 ead2 113 ead1 112 ead0 111 tclk1 101 tsync1 100 tdat1 99 tclk0 97 tsync0 95 tdat0 94 tm0 93 tm1 92 tm2 91 cbe3* 46 cbe2* 57 cbe1* 68 cbe0* 78 ad31 36 ad30 37 ad29 38 ad28 39 ad27 42 ad26 43 ad25 44 ad24 45 ad23 48 ad22 49 ad21 51 ad20 52 ad19 53 ad18 54 ad17 55 ad16 56 ad15 69 ad14 71 ad13 72 ad12 73 ad11 74 ad10 75 ad9 76 ad8 77 ad7 79 ad6 82 ad5 83 ad4 84 ad3 85 ad2 86 ad1 87 ad0 88 rdat2 11 rsync2 10 rclk2 9 roof2 8 tdat2 102 tsync2 103 tclk2 105 rdat3 7 rsync3 6 rclk3 4 roof3 2 tdat3 106 tsync3 107 tclk3 109 u5a 74f00 1 2 3 r8 0 u5b 74f00 4 5 6 u5c 74f00 9 10 8 u5d 74f00 12 13 11 component side solder side jp1 pci edge connector ~trst b1 -12v a1 +12v b2 tck a2 tms b3 gnd a3 tdi b4 tdo a4 +5v b5 +5v a5 ~inta b6 +5v a6 ~intc b7 ~intb a7 +5v b8 ~intd a8 rsvd b9 ~prsnt1 a9 +5v_io b10 rsvd a10 rsvd b11 ~prsnt2 a11 gnd b12 gnd a12 gnd b13 gnd a13 rsvd b14 rsvd a14 ~rst b15 gnd a15 +5v_io b16 clk a16 ~gnt b17 gnd a17 gnd b18 ~req a18 rsvd b19 +5v_io a19 ad30 b20 ad31 a20 +3.3v b21 ad29 a21 ad28 b22 gnd a22 ad26 b23 ad27 a23 gnd b24 ad25 a24 ad24 b25 +3.3v a25 idsel b26 ~cbe3 a26 +3.3v b27 ad23 a27 ad22 b28 gnd a28 ad20 b29 ad21 a29 gnd b30 ad19 a30 ad18 b31 +3.3v a31 ad16 b32 ad17 a32 +3.3v b33 ~cbe2 a33 ~frame b34 gnd a34 gnd b35 ~irdy a35 ~trdy b36 +3.3v a36 gnd b37 ~devsel a37 ~stop b38 gnd a38 +3.3v b39 ~lock a39 sdone b40 ~perr a40 ~sbo b41 +3.3v a41 gnd b42 ~serr a42 par b43 +3.3v a43 ad15 b44 ~cbe1 a44 +3.3v b45 ad14 a45 ad13 b46 gnd a46 ad11 b47 ad12 a47 gnd b48 ad10 a48 ad09 b49 gnd a49 ~cbe0 b52 ad08 a52 +3.3v b53 ad07 a53 ad06 b54 +3.3v a54 ad04 b55 ad05 a55 gnd b56 ad03 a56 ad02 b57 gnd a57 ad00 b58 ad01 a58 +5v_io b59 +5v_io a59 ~req64 b60 ~ack64 a60 +5v b61 +5v a61 +5v b62 +5v a62 r3 10k j1 con2 1 2 zu1 zu2 zu3 zu4 zu5 zu6 c7 .1 c9 .1 c6 .1 c11 .1 c19 .1 c12 .1 c10 .1 c1 .1 c3 .1 c20 .1 c8 .1 c13 .1 c17 .1 c18 .1 c2 .1 r20 100k u6d 74h c t 03 12 13 11 r19 100k r18 100k u6b 74hct03 4 5 6 u6c 74hct03 9 10 8 u6a 74hct03 1 2 3 r21 100k r5 0 r4 100 y1 10mhz osc. dis* 1 out 3 vcc 4 gnd 2 r9 10k r1 0 r22 10k r23 10k c61 .1 8478_062 preliminary review 8/16/99 1600
n8478ug1a appendix d : circuit schematics evaluation module user?s guide n8478ug1a conexant d-3 preliminary information/conexant proprietary and confidential figure d-2. t1/e1 interface - port 1 bt8474evm t1/e1 interface - port 1 t1/isdn-pri line termination im pedance set : 75 ohms (e1) not set : 100 o hms (t1) ead8 ead7 ead6 ead5 ead4 ead3 ead2 ead1 ead0 vcc vcc c22 .1 c23 .1 c24 .1 c25 .1 c26 .1 c27 .1 c28 .1 c21 10 c30 15p r25 12.4k r26 1k0 1% r27 240 1% j3 rj48c 1 2 3 4 5 6 7 8 r24 51.1 1% c29 100p 5% fs1 polyswitch 600v 1 2 z1 p1553ab 1 2 3 fs2 polyswitch 600v 1 2 fs4 polyswitch 600v 1 2 d1 6.2v d2 6.2v d4 6.2v l1 filter 1 2 3 4 5 6 7 8 u7 bt8370 rev d - 80mqfp vdd5 69 vdd4 60 vdd3 59 vdd2 50 vdd1 30 vdd0 7 vdd6 72 gnd6 75 gnd4 62 gnd3 56 gnd2 49 gnd1 31 gnd0 8 a0 9 a1 11 a2 13 a3 15 a4 17 a5 19 a6 21 a7 23 a8 25 ad0 10 ad1 12 ad2 14 ad3 16 ad4 18 ad5 20 ad6 22 ad7 24 wr* 6 rd*/ds* 4 cs* 2 ale/as* 5 clkmd 26 intel/moto* 78 mclk 29 rst* 28 dtack* 77 intr* 3 onesec 32 xtip 58 xring 57 xoe 79 mtip 70 mring 71 rtip 73 rring 74 vset 61 tcki 65 acki 51 tposi/tdli 41 tcko 64 tposo/tnrzo 27 tnego/msynco 39 tnegi/tdlclko 38 rcki 76 rcko 48 rposo/rdlo 47 rnego/rdlcko 46 tsbcki 37 tpcmi 34 tsigi 33 rsbcki 45 tfsync 35 tmsync 36 rpcmo 42 rsigo 40 rfsync 43 rmsync 44 sigfrz 80 cladi 67 refcki 68 tck 53 tms 52 tdi 55 clado 66 tdo 54 syncmd 1 gnd5 63 fs3 polyswitch 600v 1 2 e1 1 2 d3 6.2v tr1 t1044 6 8 3 2 1 16 15 14 11 10 9 z2 p1553ab 1 2 3 r46 100 1% r47 100 1% c62 .1 ~liusel_0 ale ~rd ~wr tdat0 eclk refclk ~reset ead[0:8] ~liu_irq rdat0 rfsync0 roof0 bclk0 tfsync0 shared_clk extclk 8478_063 preliminary review 8/16/99 1600
appendix d : circuit schematics n8478ug1a evaluation module user?s guide d-4 conexant n8478ug1a preliminary information/conexant proprietary and confidential figure d-3. t1/e1 interface - port 2 t1/isdn-pri line bt8474evm t1/e1 interface - port 2 termination im pedance set : 75 ohms (e1) not set : 100 o hms (t1) ead8 ead7 ead6 ead5 ead4 ead3 ead2 ead1 ead0 vcc vcc c32 .1 c33 .1 c34 .1 c35 .1 c36 .1 c37 .1 c38 .1 c31 10 c40 15p r31 12.4k j4 rj48c 1 2 3 4 5 6 7 8 r30 51.1 1% c39 100p 5% fs5 polyswitch 600v 1 2 fs6 polyswitch 600v 1 2 fs8 polyswitch 600v 1 2 d5 6.2v d6 6.2v l2 filter 1 2 3 4 5 6 7 8 u8 bt8370 rev d - 80mqfp vdd5 69 vdd4 60 vdd3 59 vdd2 50 vdd1 30 vdd0 7 vdd6 72 gnd6 75 gnd4 62 gnd3 56 gnd2 49 gnd1 31 gnd0 8 a0 9 a1 11 a2 13 a3 15 a4 17 a5 19 a6 21 a7 23 a8 25 ad0 10 ad1 12 ad2 14 ad3 16 ad4 18 ad5 20 ad6 22 ad7 24 wr* 6 rd*/ds* 4 cs* 2 ale/as* 5 clkmd 26 intel/moto* 78 mclk 29 rst* 28 dtack* 77 intr* 3 onesec 32 xtip 58 xring 57 xoe 79 mtip 70 mring 71 rtip 73 rring 74 vset 61 tcki 65 acki 51 tposi/tdli 41 tcko 64 tposo/tnrzo 27 tnego/msynco 39 tnegi/tdlclko 38 rcki 76 rcko 48 rposo/rdlo 47 rnego/rdlcko 46 tsbcki 37 tpcmi 34 tsigi 33 rsbcki 45 tfsync 35 tmsync 36 rpcmo 42 rsigo 40 rfsync 43 rmsync 44 sigfrz 80 cladi 67 refcki 68 tck 53 tms 52 tdi 55 clado 66 tdo 54 syncmd 1 gnd5 63 fs7 polyswitch 600v 1 2 tr2 t1044 6 8 3 2 1 16 15 14 11 10 9 z3 p1553ab 1 2 3 z4 p1553ab 1 2 3 r32 1k0 1% r33 240 1% d8 6.2v e2 1 2 d7 6.2v r48 100 1% r49 100 1% c63 .1 ~liusel_1 ale ~rd ~wr tdat1 eclk refclk ~reset ead[0:8] ~liu_irq rdat1 rfsync1 roof1 bclk1 tfsync1 shared_clk extclk 8478 064 preliminary review 8/16/99 1600
n8478ug1a appendix d : circuit schematics evaluation module user?s guide n8478ug1a conexant d-5 preliminary information/conexant proprietary and confidential figure d-4. t1/e1 interface - port 3 t1/isdn-pri line bt8474 evm t1/e1 interface - port 3 termination im pedance set : 75 ohms (e1) not set : 100 o hms (t1) ead8 ead7 ead6 ead5 ead4 ead3 ead2 ead1 ead0 vcc vcc c42 .1 c43 .1 c44 .1 c45 .1 c46 .1 c47 .1 c48 .1 c41 10 c50 15p r37 12.4k j5 rj48c 1 2 3 4 5 6 7 8 r36 51.1 1% c49 100p 5% fs9 polyswitch 600v 1 2 fs10 polyswitch 600v 1 2 fs12 polyswitch 600v 1 2 d9 6.2v d10 6.2v l3 filter 1 2 3 4 5 6 7 8 u9 bt8370 rev d - 80mqfp vdd5 69 vdd4 60 vdd3 59 vdd2 50 vdd1 30 vdd0 7 vdd6 72 gnd6 75 gnd4 62 gnd3 56 gnd2 49 gnd1 31 gnd0 8 a0 9 a1 11 a2 13 a3 15 a4 17 a5 19 a6 21 a7 23 a8 25 ad0 10 ad1 12 ad2 14 ad3 16 ad4 18 ad5 20 ad6 22 ad7 24 wr* 6 rd*/ds* 4 cs* 2 ale/as* 5 clkmd 26 intel/moto* 78 mclk 29 rst* 28 dtack* 77 intr* 3 onesec 32 xtip 58 xring 57 xoe 79 mtip 70 mring 71 rtip 73 rring 74 vset 61 tcki 65 acki 51 tposi/tdli 41 tcko 64 tposo/tnrzo 27 tnego/msynco 39 tnegi/tdlclko 38 rcki 76 rcko 48 rposo/rdlo 47 rnego/rdlcko 46 tsbcki 37 tpcmi 34 tsigi 33 rsbcki 45 tfsync 35 tmsync 36 rpcmo 42 rsigo 40 rfsync 43 rmsync 44 sigfrz 80 cladi 67 refcki 68 tck 53 tms 52 tdi 55 clado 66 tdo 54 syncmd 1 gnd5 63 fs11 polyswitch 600v 1 2 tr3 t1044 6 8 3 2 1 16 15 14 11 10 9 z5 p1553ab 1 2 3 z6 p1553ab 1 2 3 r38 1k0 1% r39 240 1% d12 6.2v e3 1 2 d11 6.2v r50 100 1% r51 100 1% c64 .1 ~liusel_2 ale ~rd ~wr tdat2 eclk refclk ~reset ead[0:8] ~liu_irq rdat2 rfsync2 roof2 bclk2 tfsync2 shared_clk extclk 8478_065 preliminary review 8/16/99 1600
appendix d : circuit schematics n8478ug1a evaluation module user?s guide d-6 conexant n8478ug1a preliminary information/conexant proprietary and confidential figure d-5. t1/e1 interface - port 4 t1/isdn-pri line bt8474evm t1/e1 interface - port 4 termination im pedance set : 75 ohms (e1) not set : 100 o hms (t1) ead8 ead7 ead6 ead5 ead4 ead3 ead2 ead1 ead0 vcc vcc c52 .1 c53 .1 c54 .1 c55 .1 c56 .1 c57 .1 c58 .1 c51 10 c60 15p r43 12.4k j6 rj48c 1 2 3 4 5 6 7 8 r42 51.1 1% c59 100p 5% fs13 polyswitch 600v 1 2 fs14 polyswitch 600v 1 2 fs16 polyswitch 600v 1 2 d13 6.2v d14 6.2v l4 filter 1 2 3 4 5 6 7 8 u10 bt8370 rev d - 80mqfp vdd5 69 vdd4 60 vdd3 59 vdd2 50 vdd1 30 vdd0 7 vdd6 72 gnd6 75 gnd4 62 gnd3 56 gnd2 49 gnd1 31 gnd0 8 a0 9 a1 11 a2 13 a3 15 a4 17 a5 19 a6 21 a7 23 a8 25 ad0 10 ad1 12 ad2 14 ad3 16 ad4 18 ad5 20 ad6 22 ad7 24 wr* 6 rd*/ds* 4 cs* 2 ale/as* 5 clkmd 26 intel/moto* 78 mclk 29 rst* 28 dtack* 77 intr* 3 onesec 32 xtip 58 xring 57 xoe 79 mtip 70 mring 71 rtip 73 rring 74 vset 61 tcki 65 acki 51 tposi/tdli 41 tcko 64 tposo/tnrzo 27 tnego/msynco 39 tnegi/tdlclko 38 rcki 76 rcko 48 rposo/rdlo 47 rnego/rdlcko 46 tsbcki 37 tpcmi 34 tsigi 33 rsbcki 45 tfsync 35 tmsync 36 rpcmo 42 rsigo 40 rfsync 43 rmsync 44 sigfrz 80 cladi 67 refcki 68 tck 53 tms 52 tdi 55 clado 66 tdo 54 syncmd 1 gnd5 63 fs15 polyswitch 600v 1 2 tr4 t1044 6 8 3 2 1 16 15 14 11 10 9 z7 p1553ab 1 2 3 z8 p1553ab 1 2 3 r44 1k0 1% r45 240 1% d16 6.2v e4 1 2 d15 6.2v r52 100 1% r53 100 1% c65 .1 ~liusel_3 ale ~rd ~wr tdat3 eclk refclk ~reset ead[0:8] ~liu_irq rdat3 rfsync3 roof3 bclk3 tfsync3 shared_clk extclk 8478_066 preliminary review 8/16/99 1600
n8478ug1a conexant e-1 preliminary information/conexant proprietary and confidential e appendix e: circuit board drawings figures e-1 through e-5 illustrate the levelss of the circuit board. figure e-5 is the silkscreen for the top level, which has all the reference designators and component outlines. preliminary review 8/16/99 1600
appendix e : circuit board drawings n8478ug1a evaluation module user?s guide e-2 conexant n8478ug1a preliminary information/conexant proprietary and confidential preliminary review 8/16/99 1600
further information literature@c onexant.com 1-800-854-8099 (north america) 33-14-906-3980 (international) web site www.conexant.com world headquarters conexant systems, inc. 4311 jamboree road p. o. box c newport beach, ca 92658-8902 phone: (949) 483-4600 fax: (949) 483-6375 u.s. florida/south america phone: (727) 799-8406 fax: (727) 799-8306 u.s. los angeles phone: (805) 376-0559 fax: (805) 376-8180 u.s. mid-atlantic phone: (215) 244-6784 fax: (215) 244-9292 u.s. north central phone: (630) 773-3454 fax: (630) 773-3907 u.s. northeast phone: (978) 692-7660 fax: (978) 692-8185 u.s. northwest/pacific west phone: (408) 249-9696 fax: (408) 249-7113 u . s. south central phone: (972) 733-0723 fax: (972) 407-0639 u.s. southeast phone: (919) 858-9110 fax: (919) 858-8669 u.s. southwest phone: (949) 483-9119 fax: (949) 483-9090 apac headquarters conexant systems singapore, pte. ltd. 1 kim seng promenade great world city #09-01 east tower singapore 237994 phone: (65) 737 7355 fax: (65) 737 9077 australia phone: (61 2) 9869 4088 fax: (61 2) 9869 4077 china phone: (86 2) 6361 2515 fax: (86 2) 6361 2516 hong kong phone: (852) 2827 0181 fax: (852) 2827 6488 india phone: (91 11) 692 4780 fax: (91 11) 692 4712 korea phone: (82 2) 565 2880 fax: (82 2) 565 1440 phone: (82 53) 745 2880 fax: (82 53) 745 1440 europe headquarters conexant systems france les taissounieres b1 1681 route des dolines bp 283 06905 sophia antipolis cedex france phone: (33 1) 41 44 36 50 fax:(334)93003303 europe central phone: (49 89) 829 1320 fax: (49 89) 834 2734 europe mediterranean phone: (39 02) 9317 9911 fax: (39 02) 9317 9913 europe north phone: (44 1344) 486 444 fax: (44 1344) 486 555 europe south phone: (33 1) 41 44 36 50 fax:(331)41443690 middle east headquarters conexant systems commercial (israel) ltd. p. o. box 12660 herzlia 46733, israel phone: (972 9) 952 4064 fax: (972 9) 951 3924 japan headquarters conexant systems japan co., ltd. shimomoto building 1-46-3 hatsudai, shibuya-ku, tokyo 151-0061 japan phone: (81 3) 5371-1567 fax: (81 3) 5371-1501 taiwan headquarters conexant systems, taiwan co., ltd. room 2808 international trade building 333 keelung road, section 1 taipei 110, taiwan, roc phone: (886 2) 2720 0282 fax: (886 2) 2757 6760 0 . 0 s a l es offi ces preliminary review 8/16/99 1600

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